Wafer level chip scale packaging (WLCSP) is currently widely used for its low cost and relatively simple processes. In a typical WLCSP, interconnect structures are formed on metallization layers, followed by the formation of under bump metallurgy (UBM), and the mounting of solder balls. FIG. 1 is a cross-sectional view of an interconnect structure known to the inventors and used in WLCSP. Chip (or wafer) 20 includes substrate 30, on which active circuit 32 is formed. Interconnect structure 40 includes a plurality of metallization layers comprising metal lines and vias (not shown). The metallization layers include a top dielectric layer in which metal pad 52 is formed. Metal pad 52 may be electrically coupled to bond pad 38 through vias 48 and routing line or redistribution layer (RDL) 46. Passivation layers 34 and 36 are formed over substrate 30 and also over interconnect structure 40. Bond pad 38 is formed over passivation layer 34 and UBM layer 41 contacts bond pad 38. Bump ball 42 is formed over and electrically connected to, and possibly contacting, UBM layer 41. Bond pad 38 has a horizontal dimension L1, which is measured in a plane parallel to the front surface (the surface facing up in FIG. 1) of substrate 30. TAW layer 41 has dimension L2, which is measured in the same direction as the direction of horizontal dimension L1. To reduce the adverse effect of warpage and therefore delamination in chip 20, generally dimension L1 of bond pad 38 is larger than dimension L2 of UBM layer 41. A top view of a bond pad design 22 of the structure shown in FIG. 1 is illustrated in FIG. 2.
Because of their size, bond pads 38 occupy a significant percentage of the chip surface. As bond pads 38 have circular shapes and with the increasingly higher density of semiconductor devices, the size of the circular bond pads 38 may limit the number of routing lines or RDLs 46 for routing. If there are too many routing lines per a given area, there is a risk of bridging or causing a short circuit.
By decreasing the size of the circular bond pads 38, a designer can provide more spacing between adjacent bond pads 38 for routing. FIG. 3 shows an example of a bond pad design 22 where dimension L1 of bond pad 38 is smaller than dimension L2 of UBM layer 41. This design allows for an extra routing line to go between adjacent bond pads 38 as compared to the design depicted in FIG. 2. However, chips having such designs are prone to delamination from warpage and/or thermal cycle stress. Stress may be imparted to interconnect structure 40 through bond pad 38, potentially causing the low-k dielectric layers to delaminate in interconnect structure 40. When the size of bond pad 38 is decreased, more stress is imparted to interconnect structure 40 because there is reduced support for UBM layer 41; hence the reliability of the resulting package is made worse. The delamination is particularly severe at the corners 15 of chip 20. To reduce the risk of delamination, typically dimension L1 of bond pad 38 is made larger than dimension L2 of UBM layer 41 by a predetermined amount.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved bond pad design that provides for additional routing whilst reducing package stress.